PowerVia moves a chip’s power delivery network beneath the silicon, reducing the size of logic cells and cutting power consumption. Kelleher says Intel is on track to introduce a technology it calls PowerVia ( backside power delivery, more generally) in 2024. But interconnect technology will probably see the biggest change. Future semiconductor process technology has to contend with the thermal stresses of a 3D-packaged environment. The drive to optimize systems by disaggregating functions is having consequences for future semiconductor manufacturing processes. Reducing the bond pitch to between 2 micrometers and 100 nanometers could mean being able to start pulling apart logic functions that today must be on the same piece of silicon, according to Kelleher. With that, even more cache can be separated from the processor cores. Hybrid bond pitches, meaning the distance between the interconnects, are just 3 micrometers with this new technology. Increased connection density means more chip functions can be disaggregated onto separate chiplets, in turn providing more potential to use STCO to improve outcomes. IntelĪt IEDM, Intel engineers will report that they’ve increased the density of their 3D hybrid bonding technology tenfold versus what they reported in 2021. Intel sees a concept called system technology co-optimizaiton as the next phase of Moore’s Law. “It brings together silicon from different fabs and enables them to come together so that the system is able to perform against the workload that it’s designed for,” she says. These are stitched together using both advanced horizontal connections (2.5D packaging tech) and 3D stacking. ![]() It’s composed of 47 active chiplets (as well as 8 blanks for thermal conduction). So it makes sense to build SRAM caches and compute cores as separate chiplets using different process technology and then stitch them together using 3D integration.Ī key example of STCO in action, says Kelleher, is the Ponte Vecchio processor at the heart of the Aurora supercomputer. For example, Kelleher points out in her plenary that high-performance computing demands a large amount of cache memory per processor core, but chipmaker’s ability to shrink SRAM is not proceeding at the same pace as the scaling down of logic. This means that what would once be functions on a single chip can be disaggregated onto dedicated chiplets, which can each then be made using the most optimal semiconductor process technology. STCO is an option now in large part because advanced packaging, such as 3D integration, is allowing the high-bandwidth connection of chiplets-small, functional chips-inside a single package. “With system technology co-optimization, it means all the pieces are optimized together so that you’re getting your best answer for the end product,” she says. It starts with the workload a product needs to support and its software, then works down to system architecture, then what type of silicon must be within a package, and finally down to the semiconductor manufacturing process. Kelleher calls it an “outside-in” manner of development. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference. “As we look forward into the next 10 to 20 years, there’s a pipeline full of innovation” that will continue the cadence of improved products every two years. “Moore’s Law is about increasing the integration of functions,” says Kelleher. Kelleher, general manager of technology development at Intel in an interview with IEEE Spectrum ahead of her plenary talk at the 2022 IEEE Electron Device Meeting (IEDM). The next wave of Moore’s Law will rely on a developing concept called system technology co-optimization, said Ann B.
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